The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
Multi-core systems with per-core caches and a single shared memory addressing space face the problem of inconsistent data. In such systems, multiple caches may store separate copies of the same memory block. When a core updates data within the memory block, then previously cached versions of the memory block become invalid. Without cache coherence, there is a possibility that invalid data will be provided from a cache to one of the cores.
Multi-core systems typically employ hardware-based devices that enforce cache coherence and prevent cores from operating on invalid data. Hardware-based approaches provide a relatively fast and effective solution to the cache coherence problem. However, as the number of cores and caches increase within a multi-core system, the level of complexity, power consumption, and amount of silicon real estate required by coherence-enforcing hardware also increase. These factors raise cost concerns and present implementation challenges when trying to scale the hardware-based approach to larger and larger systems.
To reduce costs associated with the hardware-based approach, hybrid solutions have been proposed. These solutions generally involve software-based enforcement of coherence with some hardware support. According to one such approach, software is responsible for triggering and otherwise managing coherence actions, while Bloom filters are implemented in hardware to invalidate incoherent data. Hybrid solutions generally cannot perform at the same speed as fully hardware-based solutions. However, the hybrid solutions may be easier to scale, attempting to trade as little performance for as much reduction of power and silicon area as possible.